1. Field of the Invention
The invention relates to the routing of electrical signals in a computing system, and more specifically, to a pathway for carrying clock signals to an integrated circuit chip and on to a termination.
2. Description of the Related Art
In a computing system, various circuit components must often work in a coordinated fashion to carry out a specified function. Examples of such components include processors and memory and I/O (input/output) controller chips. Coordination of these circuit components is enabled by running the components off the same system clock. The traces representative of the system clock are routed to each of these circuit components along a signal pathway formed on a circuit board of the computing system.
It is desirable to have a termination formed at the end of the signal pathway when routing relatively fast clock signals (e.g., around 250 MHz-300 MHZ+). The termination may be an xe2x80x9cactivexe2x80x9d termination comprising a circuit specifically designed to handle clock signals in a given speed range, or a xe2x80x9cpassive terminationxe2x80x9d, for example comprising merely one or more resistors. The function of the termination is to attenuate signal noise generated in the pathway by signal reflections of such fast clock signals. As computer system and component architecture has evolved, circuit components that receive clock signals are more commonly designed with a termination within the component (or the associated package) itself. This is often the best scenario for minimizing unwanted signal noise. However, certain circuit components have been designed without such a termination formed thereon; the termination is either omitted altogether, which is undesirable, or is placed on the circuit board at a location along the signal pathway. Also, when the termination is formed off of the circuit component, a stub is formed in the signal pathway, which represents the part of the pathway where clock signals are carried in both directions (i.e., to and from the component). As a general rule, as the speed of the clock signals increase, a shorter stub is required such that signal reflections and signal quality distortion is minimized.
One potential signal pathway 10 design with termination is shown in FIG. 1, for a memory and I/O controller chip unit 12 mounted onto a surface 13 of a circuit board 14. The memory and I/O controller chip unit 12 comprises a package 16 and an integrated circuit chip 18, or die, mounted with the package. The signal pathway 10 originates at a first end 20 electrically coupled with a clock signal driver (not shown) mounted on the circuit board 14. The signal pathway 10 is routed on the circuit board 14 and extends across an interface 22 (e.g., a ball grid array) between the circuit board 14 and the chip unit 12 onto the package 16 and to the circuit chip 18 to form a second end 24. A resistive termination 26 is placed along the signal pathway 10 between the first end 20 and the interface 22, thereby forming a stub 28 of the pathway 10 between the termination 26 and the pathway second end 24. A clock signal generated by the signal driver would travel from the first end 20 along the signal pathway 10 to the circuit chip 18 at the second end 24, and return along the pathway to the resistive termination 26. Because the interface 22 is formed as a ball grid, it is not possible to place the resistive termination 26 at that location. Additionally, a xe2x80x9ckeepoutxe2x80x9d area 30 is commonly required around the perimeter of the chip unit 12 on the circuit board surface 13, such that the resistive termination 26 must be further spaced away from the pathway second end 24. Thus, the signal pathway 10 shown in FIG. 1 forms a stub 28 that is excessively long for use with relatively fast clock signals. Depending on the particular memory and I/O controller chip unit 12 chosen, the stub 28 could exceed 35 mm in length.
FIG. 3 shows another signal pathway SO design with termination that could potentially be used to route clock signals in a computing system. Similar to FIG. 1, a memory and I/O controller chip unit 52 is mounted onto a surface 53 of a circuit board 54, and comprises a package 56 and an integrated circuit chip 58 mounted therewith. The signal pathway 50 is routed along the circuit board 54 from a first end 60 thereof electrically coupled with a clock signal driver to a second end 62 thereof where a resistive termination 64 is formed. A stub base 66 is formed on the signal pathway 50 from which a stub 68 extends across a single pad 70 of a ball grid array interface 72 between the circuit board 54 and the chip unit 52 to the circuit chip 58. A clock signal generated by the signal driver would travel from the first end 60 along the signal pathway 10 to stub 68, reaching the circuit chip 58, and returning back to the stub base 66 and onto the resistive termination 64 at the second end 62.
The signal pathway 50 of FIG. 3 is preferred to the pathway 10 of FIG. 1 for two reasons. First, the resistive termination 64 of the signal pathway 50 of FIG. 3 is at the end of the pathway 50, as opposed to being in the middle of the pathway, as with signal pathway 10 of FIG. 1. Second, the stub 68 of the signal pathway 50 of FIG. 2 is shorter than the stub 28 of signal pathway 10 of FIG. 1. Both of these features provide improved signal noise attenuation in signal pathway 50 of FIG. 3 over signal pathway 10 of FIG. 1. However, in computing systems utilizing relatively fast clock signals, the stub 68 of the signal pathway 50 of FIG. 3 remains often unacceptably long, leading to compromised signal integrity. Therefore, providing a solution for a signal pathway design that carries clock signals to a circuit component in a computing system and effectively controls unwanted signal noise has remained elusive.
The present invention provides a signal pathway having a termination and being configured to deliver clock signals to a circuit component mounted with a circuit board. The signal pathway has separate signal lines formed on the circuit hoard, which each extend to a separate terminal for electrical coupling with a circuit component. The signal lines of the circuit board are themselves electrically connected together with one or more signal lines formed on the circuit component by extending from one pad interfaced with the terminal of one circuit board signal line to another pad interfaced with the terminal of another circuit board signal line. One of the signal lines on the circuit board is considered a xe2x80x9cSignal Inxe2x80x9d line, and has an end opposite of the interface terminal that is connected with a clock driver. Another signal line on the circuit board is likewise considered a xe2x80x9cSignal Outxe2x80x9d line, and has an end opposite of the interface terminal that is connected with a termination.
In one aspect, the circuit component comprises a package and an integrated circuit chip mounted with the package, with the signal line of the circuit component being routed on the package. A stub extends from the signal line on the package to carry the clock signal to the integrated circuit chip, and back to the signal line for routing on to the Signal Out line on the circuit board. The speed of the clock signals will dictate the desired length for the stub. For example, clock signals having a frequency of at least about 250 MHz should, preferably, require a stub length of about 2 mm or less to maintain acceptable clock signal integrity.
In another aspect, the termination on the Signal Out line is a resistive termination comprising one or more resistors. The resistive termination preferably has an impedance that matches the impedance of the signal pathway.
Thus, the signal pathway of the present invention provides an improved route for carrying clock signals to a circuit component while providing proper termination of such signals on a circuit board. The signal pathway design facilitates the attenuation of unwanted noise in the signals when a termination is not incorporated into the design of the particular circuit component.